The present invention relates generally to methods of forming metal plugs within vias used in the formation of semiconductor devices and specifically to a method of eliminating metal corrosion by FSG (fluorinated silica glass).
Semiconductor devices constantly decrease in size with more and more devices, of a smaller and smaller design rule, per fabricated wafer. Interconnect layers, usually formed of FSG, are formed over the devices. Via openings are formed within the interconnect layers and are filled with metal plugs to form electrical connections with the underlying layers.
U.S. Pat. No. 5,937,323 to Orczyk et al. describes a method of forming a fluorinated silicon glass (FSG) layer on a substrate. An undoped silicon glass (USG) liner under the FSG layer protects the substrate from corrosive attack.
U.S. Pat. No. 5,908,672 to Ryu et al. describes a planarized passivation layer that includes an FSG layer and a silicon nitride layer. The FSG layer is preferably deposited using triethoxyfluorosilane (TEFS) and tetraethoxyorthosilicate (TEOS).
U.S. Pat. No. 5,858,869 to Chen et al. describes a method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity. Metal lines are formed and an anisotropic plasma oxide (APO) is deposited thereover, lining the sidewalls and upper surface of the metal lines. A low k polymer is deposited over the APO and the polymer and the APO are CMP""ed back to the top of the metal lines. An FSG layer is deposited and via holes are etched in the FSG layer. The APO provides wider openings between metal lines filled with the low k polymer.
U.S. Pat. No. 5,759,906 to Lou describes a method of forming a planar intermetal dielectric layer (IMD) for multilevel electrical interconnections on ULSI circuits. After via holes are etched in the IMD, an FSG insulating layer is deposited and etched back to form sidewall spacers in the via holes to prevent outgassing from the SOG or lowxe2x80x94k polymer.
Accordingly, it is an object of the present invention to provide a method of forming metal plugs within via openings that eliminates metal corrosion by FSG film.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor substrate having an overlying metal layer and oxide hard masks overlying the metal layer is provided. The oxide hard masks are used to etch the metal layer to form metal lines separated by metal line openings. An oxide liner is formed over the etched structure. A layer of FSG is deposited over the oxide liner. The FSG layer is then planarized to remove: the excess of the FSG layer from the etched structure; and the portions of the oxide liner over the oxide hard masks to form FSG blocks within the metal line openings. A cap layer is formed over the planarized structure. The cap layer and hard masks are then planarized to form via openings exposing the metal lines. Planarized metal plugs are then within the via openings.